`timescale 1ns / 1ps

module rgmii_send(
     input wire         reset,
	 input wire         RGMII_reference_clk,
	 input wire         RGMII_reference_clk_90,
	 //input        mac_tx_error,
	 input wire         mac_tx_data_valid,
	 input wire [7:0]   mac_tx_data,
	 
	 output wire        RGMII_tx_clk,
	 output wire        RGMII_tx_ctrl,
	 output wire [3:0]  RGMII_tx_data 
    );

EG_LOGIC_ODDR rgmii_txc_ddr(
        .q		(RGMII_tx_clk),
        .clk	(RGMII_reference_clk_90),
        .d1		(1'b0),
        .d0		(1'b1),
        .rst	(reset)
);

EG_LOGIC_ODDR rgmii_ctl_ddr(
        .q		(RGMII_tx_ctrl),
        .clk	(RGMII_reference_clk),
        .d1		(mac_tx_data_valid ^ 1'b0),
        .d0		(mac_tx_data_valid),
        .rst	(reset)
);

genvar j;
generate for (j=0; j<4; j=j+1)
    begin : RGMII_TX_DATA_BUS	
		EG_LOGIC_ODDR rgmii_data_ddr(
			.q		(RGMII_tx_data[j]		),
			.clk	(RGMII_reference_clk	),
			.d1		(mac_tx_data[j+4]		),
			.d0		(mac_tx_data[j]			),
			.rst	(reset					)
		);		
	end
endgenerate
	 
endmodule
